Non-volatile memory device and method of operating the same

ABSTRACT

A method of operating a non-volatile memory device includes performing a first sensing operation on the non-volatile memory device during a first sensing time including a first section, a second section, and a third section. The performing of the first sensing operation includes applying a first voltage level, which is variable according to a first target voltage level, to a selected word line in the first section, applying a second voltage level, which is different from the first voltage level, to the selected word line in the second section, and applying the first target voltage level, which is different from the second voltage level, to the selected word line in the third section. The first voltage level becomes greater as the first target voltage level becomes greater.

CROSS-REFERENCE TO RELATED APPLICATION

This application is a continuation-in-part of U.S. application Ser. No.16/547,416, filed on Aug. 21, 2019, which claims the benefit of KoreanPatent Application No. 10-2018-0160352, filed on Dec. 12, 2018, in theKorean Intellectual Property Office, the disclosure of each of which isincorporated herein in its entirety by reference.

BACKGROUND

The inventive concept relates to a memory, and more particularly, to anon-volatile memory device and a method of operating the same.

Memory devices are used to store data and may be classified as eithervolatile memory devices or non-volatile memory devices. A flash memorydevice, which is an example of a non-volatile memory device, may beemployed in portable phones, digital cameras, personal digitalassistants (PDAs), transportable computer devices, fixed computerdevices, and other devices. Recently, as information communicationdevices have become more multifunctional, it has become more necessaryto increase the capacity and integration density of memory devices.

SUMMARY

The inventive concept provides a non-volatile memory device, which mayreduce a word line setup time and improve sensing performance, and amethod of operating the device.

According to an aspect of the inventive concept, there is provided amethod of operating a non-volatile memory device. The method includesperforming a first sensing operation on the non-volatile memory deviceduring a first sensing time including a first section, a second section,and a third section. The performing of the first sensing operationincludes applying a first voltage level, which is variable according toa first target voltage level, to a selected word line in the firstsection, applying a second voltage level, which is different from thefirst voltage level, to the selected word line in the second section,and applying the first target voltage level, which is different from thesecond voltage level, to the selected word line in the third section.The first voltage level becomes greater as the first target voltagelevel becomes greater.

According to another aspect of the inventive concept, there is provideda method of operating a non-volatile memory device. The method includesperforming a first sensing operation on the non-volatile memory deviceduring a first sensing time including a first section, a second section,and a third section. The performing of the first sensing operationincludes applying a first voltage level to a selected word line in thefirst section, a duration of which is variable according to a firsttarget voltage level, applying a second voltage level, which isdifferent from the first voltage level, to the selected word line in thesecond section, and applying the first target voltage level, which isdifferent from the second voltage level, to the selected word line inthe third section. A duration of the first section becomes longer as thefirst target voltage level becomes greater.

According to another aspect of the inventive concept, there is provideda method of operating a non-volatile memory device. The method includesperforming a first sensing operation on the non-volatile memory deviceduring a first sensing time, and performing a second sensing operationon the non-volatile memory device during a second sensing time after thefirst sensing time. The performing of the first sensing operationincludes applying a first voltage level to a selected word line in afirst section of the first sensing time, applying a second voltage levelto the selected word line in a second section of the first sensing time,which follows the first section of the first sensing time, wherein thesecond voltage level is different from the first voltage level, andapplying a first target voltage level to the selected word line in athird section of the first sensing time, which follows the secondsection of the first sensing time, wherein the first target voltagelevel is different from the second voltage level. As the first targetvoltage level becomes greater, a duration of the first section becomeslonger or the first voltage level becomes greater.

According to another aspect of the inventive concept, there is provideda non-volatile memory device including a memory cell array including amemory cell and a selected word line connected to the memory cell, acontrol logic circuit configured to divide a sensing time for which asensing operation is performed on the memory cell, into a first section,a second section, and a third section, determine a selected word linevoltage applied to the selected word line to be a first voltage level inthe first section, determine the selected word line voltage to be asecond voltage level in the second section, determine the selected wordline voltage to be a target voltage level in the third section, anddetermine at least one of a duration of the first section and the firstvoltage level according to the target voltage level, wherein the secondvoltage level is different from the first voltage level, and the targetvoltage level is different from the second voltage level, and a voltagegenerator configured to generate the second word line voltage in thefirst to third sections.

According to yet another aspect of the inventive concept, there isprovided a non-volatile memory device including a memory cell arraycomprising a plurality of word lines and memory cells each connected toone of the word lines; a control logic circuit; and a voltage generator.The control logic circuit is configured to select a selected word lineamong the plurality of word lines in response to an address received bythe control logic circuit, to determine a target voltage level to beapplied to the selected word line as a selected word line voltage for asensing operation during a first sensing time in order to perform amemory operation on a selected memory cell connected to the selectedword line, the control logic circuit further configured to: cause theselected word line voltage to be a first voltage level in a firstsection of the first sensing time, cause the selected word line voltageto be a second voltage level in a second section of the first sensingtime which immediately follows the first section of the first sensingtime, wherein the second voltage is different than the first voltagelevel, and cause the selected word line voltage to be the target voltagelevel in a third section of the first sensing time which immediatelyfollows the second section of the first sensing time, wherein the targetvoltage level is different than the second voltage level. The voltagegenerator is configured to generate the selected word line voltage inthe first, second, and third sections of the sensing time in response tothe control logic circuit.

BRIEF DESCRIPTION OF THE DRAWINGS

Embodiments of the inventive concept will be more clearly understoodfrom the following detailed description taken in conjunction with theaccompanying drawings.

FIG. 1 is a block diagram of an embodiment of a non-volatile memorydevice.

FIG. 2 is a diagram of an embodiment of a memory cell array.

FIG. 3 is an equivalent circuit diagram of an embodiment of a memoryblock.

FIG. 4 is a perspective view of the memory block of FIG. 3, according toan embodiment.

FIG. 5 is a diagram of a word line driving operation according to anembodiment.

FIGS. 6A and 6B are graphs showing threshold voltage distributions ofmemory cells, according to embodiments.

FIGS. 7, 8, 9, 10 and 11 are diagrams showing word line drivingoperations according to embodiments.

FIG. 12 is a diagram showing a word line driving operation when aplurality of sensing operations is performed on an embodiment of anon-volatile memory device.

FIG. 13 is a graph showing a program operation of an embodiment of anon-volatile memory device.

FIGS. 14, 15, 16 and 17 are flowcharts of methods of operatingnon-volatile memory devices, according to embodiments.

FIGS. 18 and 19 are block diagrams of embodiments of non-volatile memorydevices.

FIG. 20 is a block diagram of an example of applying an embodiment of amemory device to a solid-state drive (SSD) system.

FIG. 21 illustrates a memory device having a chip-to-chip structure,according to embodiments.

DETAILED DESCRIPTION OF THE EMBODIMENTS

The inventive concept will now be described more fully hereinafter withreference to the accompanying drawings, in which embodiments are shown.

FIG. 1 is a block diagram of an embodiment of a non-volatile memorydevice 100.

Referring to FIG. 1, non-volatile memory device 100 may include a memorycell array 110, a control logic circuit 120, a voltage generator 130, arow decoder 140, and a page buffer unit 150. Although not shown in FIG.1, non-volatile memory device 100 may further include a datainput/output (I/O) circuit or an I/O interface. Also, non-volatilememory device 100 may further include a column logic circuit, a voltagegenerator, a pre-decoder, a temperature sensor, a command decoder, andan address decoder. Here, each of the control logic circuit 120 andcolumn logic circuit may be implemented by discrete logic elements, byan application specific integrated circuit (ASIC), by a combination of amemory that stores instructions and a processor that executes theinstructions, or by any combination of these devices.

Memory cell array 110 may be connected to page buffer unit 150 throughbit lines BL and connected to row decoder 140 through word lines WL,string selection lines SSL, and ground selection lines GSL. Memory cellarray 110 may include a plurality of memory cells. For example, thememory cells may be flash memory cells. Hereinafter, an example in whichthe plurality of memory cells are NAND flash memory cells will bedescribed in detail with reference to embodiments. However, embodimentsare not limited thereto. In some embodiments, the plurality of memorycells may be resistive memory cells, such as resistive random accessmemory (ReRAM) cells, phase-change RAM (PRAM) cells, or magnetic RAM(MRAM) cells.

In an embodiment, memory cell array 110 may include a three-dimensional(3D) memory cell array. The 3D memory cell array may include a pluralityof NAND strings, each of which may include memory cells connectedrespectively to word lines that are vertically stacked on a substrate,as described in detail below with reference to FIGS. 2 to 4. Thefollowing patent documents, which are hereby incorporated by reference,disclose suitable configurations for 3D memory arrays, in which the 3Dmemory array is configured at a plurality of levels, with word linesand/or bit lines shared between levels: U.S. Pat. Nos. 7,679,133;8,553,466; 8,654,587; 8,559,235; and U.S. Pat. Pub. No. 2011/0233648.However, embodiments are not limited thereto. In some embodiments,memory cell array 110 may include a two-dimensional (2D) memory cellarray, which may include a plurality of NAND strings arranged in a rowdirection and a column direction.

FIG. 2 is a diagram of an embodiment of a memory cell array 110.

Referring to FIG. 2, memory cell array 110 may include a plurality ofmemory blocks BLK1 to BLKi, and i may be a positive integer. Each of theplurality of memory blocks BLK1 to BLKi may have a three-dimensional(3D) structure (or a vertical structure). Specifically, each of theplurality of memory blocks BLK1 to BLKi may include a plurality of NANDstrings extending in a vertical direction VD. In this case, theplurality of NAND strings may be provided a predetermined distance apartfrom each other in first and second horizontal directions HD1 and HD2.The plurality of memory blocks BLK1 to BLKi may be selected by rowdecoder 140. For example, row decoder 140 may select a memory block,among the memory blocks BLK1 to BLKi, corresponding to a block address.

FIG. 3 is an equivalent circuit diagram of an embodiment of a memoryblock BLK. For example, the memory block BLK may correspond to one ofthe plurality of memory blocks BLK1 to BLKi of FIG. 2.

Referring to FIG. 3, the memory block BLK may include a plurality ofNAND strings (e.g., NS11 to NS33), a plurality of word lines (e.g., WL1to WL8), a plurality of bit lines (e.g., BL1 to BL3), a plurality ofground selection lines (e.g., GSL1 to GSL3), a plurality of stringselection lines (e.g., SSL1 to SSL3), and a common source line CSL.Here, the number of NAND strings, the number of word lines, the numberof bit lines, the number of ground selection lines, and the number ofstring selection lines may be variously changed according to anembodiment.

NAND strings NS11, NS21, and NS31 may be provided between a first bitline BL1 and the common source line CSL, NAND strings NS12, NS22, andNS32 may be provided between a second bit line BL2 and the common sourceline CSL, and NAND strings NS13, NS23, and NS33 may be provided betweenthe third bit line BL3 and the common source line CSL. Each NAND string(e.g., NS11) may include a string selection transistor SST, a pluralityof memory cells MC1 to MC8, and a ground selection transistor GST, whichmay be connected in series.

The string selection transistor SST may be connected to the stringselection lines SSL1 to SSL3 corresponding thereto. The memory cells MC1to MC8 may be connected to the word lines WL1 to WL8 respectivelycorresponding thereto. The ground selection transistor GST may beconnected to the ground selection lines GSL1 to GSL3 correspondingthereto. The string selection transistor SST may be connected to the bitlines BL1 to BL3 corresponding thereto, and the ground selectiontransistor GST may be connected to the common source line CSL.

In the present embodiment, word lines (e.g., WL1) located at the samelevel may be connected in common to one another, the string selectionlines SSL1 to SSL3 may be separated from one another, and the groundselection lines GSL1 to GSL3 may be separated from one another. AlthoughFIG. 3 illustrates an example in which word lines located at the samelevel are shared among the three string selection lines SSL1 to SSL3,embodiments are not limited thereto. In an example, word lines locatedat the same level may be shared between two string selection lines. Inanother example, word lines located at the same level may be sharedamong four string selection lines.

Although FIG. 3 illustrates a case in which each of the plurality ofNAND strings NS11 to NS33 includes one string selection transistor SSTand one ground selection transistor GST, embodiments are not limitedthereto. In an embodiment, each of the plurality of NAND strings NS11 toNS33 may include a plurality of string selection transistors and oneground selection transistor GST. In this case, the memory block BLK mayfurther include a plurality of string selection lines stacked in thevertical direction VD. In an embodiment, each of the plurality of NANDstrings NS11 to NS33 may include one string selection transistor SST anda plurality of ground selection transistors. In this case, the memoryblock BLK may further include a plurality of ground selection linesstacked in the vertical direction VD. In an embodiment, each of theplurality of NAND strings NS11 to NS33 may include a plurality of stringselection transistors and a plurality of ground selection transistors.In this case, the memory block BLK may further include a plurality ofstring selection lines stacked in the vertical direction VD and aplurality of ground selection lines stacked in the vertical directionVD.

FIG. 4 is a perspective view of the memory block BLK of FIG. 3,according to an embodiment.

Referring to FIG. 4, the memory block BLK may be formed in aperpendicular direction to a substrate SUB. The substrate SUB may be ofa first conductivity type (e.g., p type), and a common source line CSLmay be provided on the substrate SUB. The common source line CSL mayextend in the second horizontal direction HD2 and be doped withimpurities of a second conductivity type (e.g., n type). A plurality ofinsulating layers IL may extend in the second horizontal direction HD2and be sequentially provided in the vertical direction VD on a region ofthe substrate SUB between two adjacent common source lines CSL. Also,the plurality of insulating layers IL may be spaced a specific distanceapart from one another in the vertical direction VD. For example, theplurality of insulating layers IL may include an insulating material,such as silicon oxide.

A plurality of pillars P, each of which may be provided on a region ofthe substrate SUB between two adjacent common source lines CSL, may besequentially located in the first horizontal direction HD1 and penetratethe plurality of insulating layers IL in the vertical direction VD. Forexample, the plurality of pillars P may penetrate the plurality ofinsulating layers IL and contact the substrate SUB. Specifically, asurface layer S of each of the pillars P may include a silicon materialof the first conductivity type and function as a channel region.Meanwhile, an inner layer I of each of the pillars P may include aninsulating material, such as silicon oxide, or an air gap.

A charge storage layer CS may be provided in a region between twoadjacent common source lines CSL along exposed surfaces of theinsulating layers IL, the pillars P, and the substrate SUB. The chargestorage layer CS may include a gate insulating layer (or referred to asa ‘tunneling insulating layer’), a charge trap layer, and a blockinginsulating layer. For example, the charge storage layer CS may includean oxide-nitride-oxide (ONO) structure. Also, gate electrodes GE, suchas the selection lines GSL and SSL and the word lines WL1 to WL8, may beprovided in a region between two adjacent common source lines CSL on anexposed surface of the charge storage layer CS.

Drains or drain contacts DR may be provided on the plurality of pillarsP, respectively. For example, the drains or drain contacts DR mayinclude a silicon material doped with impurities of the secondconductivity type. Bit lines BL1 to BL3 may be provided on the drainsDR. The bit lines BL1 to BL3 may extend in the first horizontaldirection HD1 and be spaced a specific distance apart from one anotherin the second horizontal direction HD2.

When the memory cell array 110 of non-volatile memory device 100 is a 3Dmemory cell array as shown in FIGS. 2-4, the number of word lines WL1 toWL8 vertically stacked on the substrate SUB may be increased to improvethe integration density of non-volatile memory device 100. As the numberof word lines WL1 to WL8 vertically stacked on the substrate SUBincreases, a distance between the word lines WL1 to WL8 may be reduced.As a result, parasitic capacitances of a plate type between the wordlines WL1 to WL8 may be increased. Since a loading time of the wordlines WL1 to WL8 corresponds to the product of a resistance and acapacitance, the loading time of the word lines WL1 to WL8 may increasewith an increase in capacitance.

The increase in the loading time of the word lines WL1 to WL8 may leadto an increase in time taken for a sensing operation (e.g., a readoperation, a program verification operation, or an erase verificationoperation) on non-volatile memory device 100. Thus, the sensingperformance of non-volatile memory device 100 may be reduced.Accordingly, to improve both the integration density and performance ofnon-volatile memory device 100, a method of increasing the number ofword lines WL1 to WL8 vertically stacked on the substrate SUB andreducing the loading time of the word lines WL1 to WL8 may be required.

Referring back to FIG. 1, to reduce the loading time of the word lines,when control logic circuit 120 performs a sensing operation on memorycell array 110, a selection voltage applied to a selected word lineconnected to a selected memory cell may be controlled in three stages.Specifically, control logic circuit 120 may divide a sensing time forwhich the sensing operation is performed, into a first section orinterval, a second section or interval, and a third section or interval,and may determine voltage levels of the selection voltage in the firstto third sections. Here, the first and second sections may correspond toa word line setup time for setting a selection voltage to a targetvoltage level required to perform the sensing operation, and the thirdsection may correspond to a time for applying a target voltage level tothe selected word line. The word line driving operation will bedescribed in detail below with reference to FIG. 5.

In addition, control logic circuit 120 may output various controlsignals (e.g., a voltage control signal CTRL_vol, a row address X-ADDR,and a column address Y-ADDR) for programming data to memory cell array110, reading data from memory cell array 110, or erasing data stored inmemory cell array 110, based on a command CMD, an address ADDR, and acontrol signal CTRL. Thus, control logic circuit 120 may generallycontrol various operations of non-volatile memory device 100.

Voltage generator 130 may generate various kinds of voltages forperforming program, read, and erase operations on memory cell array 110based on the voltage control signal CTRL_vol. Specifically, voltagegenerator 130 may generate a word line voltage VWL, for example, aprogram voltage, a read voltage, a pass voltage, an erase verificationvoltage, or a program verification voltage. Also, voltage generator 130may further generate a string selection line voltage and a groundselection line voltage based on the voltage control signal CTRL_vol.

In an embodiment, when voltage generator 130 performs the sensingoperation on memory cell array 110, voltage generator 130 may provide aword line voltage VWL having a first voltage level to the selected wordline in the first section of the sensing time, provide a word linevoltage VWL having a second voltage level to the selected word line inthe second section of the sensing time, and provide a word line voltageVWL having a target voltage level to the selected word line in the thirdsection of the sensing time. The second voltage level may be differentfrom the first voltage level, and the target voltage level may bedifferent from the second voltage level. Also, when voltage generator130 performs a sensing operation on memory cell array 110, a passvoltage Vpass may be provided to an adjacent word line adjacent to theselected word line.

Row decoder 140 may select one of a plurality of memory blocks inresponse to the row address X-ADDR, select one of the word lines WL ofthe selected memory block, and select one of a plurality of stringselection lines SSL. Page buffer unit 150 may select some of the bitlines BL in response to the column address Y-ADDR. Specifically, pagebuffer unit 150 may operate as a write driver or a sense amplifieraccording to an operation mode.

FIG. 5 is a diagram of a word line driving operation according to anembodiment.

Referring to FIGS. 1 and 5, a sensing time 20 taken for a sensingoperation on non-volatile memory device 100 may be divided into a firstsection 21, a second section 22, and a third section 23. In anembodiment, the sensing operation may correspond to a read operation. Inan embodiment, the sensing operation may correspond to a programverification operation. In an embodiment, the sensing operation maycorrespond to an erase verification operation. However, embodiments arenot limited thereto, and the sensing operation may include arbitraryoperations for detecting a state of a memory cell, for example, athreshold voltage of the memory cell.

Control logic circuit 120 may control a selected word line voltageV_WLsel, which is applied to a selected word line connected to aselected memory cell, as shown by a curve 210 to sense a state of theselected memory cell during sensing time 20. Here, curve 210 shows avoltage level applied to the selected word line with respect to time.Control logic circuit 120 may control the selected word line voltageV_WLsel in three stages. Thus, sensing time 20 may be divided into firstsection 21, second section 22, and third section 23.

In an embodiment, when a target voltage level V_T is greater than orequal to a critical voltage level, control logic circuit 120 may controlthe selected word line voltage V_WLsel in three stages as shown by curve210. The critical voltage level may be a predetermined voltage level. Insome embodiments, the critical voltage level may be determineddifferently for each word line, each memory block, each memory plane, oreach memory chip. In some embodiments, the critical voltage level may bedetermined differently according to a number of data bits written to aselected memory cell, temperature information, a count of cycles ofprogram/erase operations on the selected memory cell, a number ofprogram loops, a threshold voltage of the selected memory cell, athreshold voltage of an adjacent memory cell adjacent to the selectedmemory cell, or an operation mode of the non-volatile memory device.When the target voltage level V_T is less than the critical voltagelevel, control logic circuit 120 may control the selected word linevoltage V_WLsel in two stages. For example, control logic circuit 120may control the selected word line voltage V_WLsel to omit first section21.

Control logic circuit 120 may control an adjacent word line voltageV_WLadj, which is applied to an adjacent word line adjacent to theselected word line during sensing time 20, as shown by a curve 220.Here, curve 220 shows a voltage level applied to the adjacent word linewith respect to time. For example, when the selected word line is a wordline WL4 of FIG. 4, the adjacent word line may be a word line WL3 or WL5of FIG. 4. A pass voltage Vpass may be applied to the adjacent word lineduring sensing time 20. The pass voltage Vpass may be greater than thetarget voltage level V_T. A first time Ta may correspond to a voltagerise time of the adjacent word line, and a second time Tb may correspondto a time for which the pass voltage Vpass is applied to the adjacentword line.

FIGS. 6A and 6B are graphs showing threshold voltage distributions ofmemory cells, according to embodiments.

Referring to FIG. 6A, the abscissa denotes a threshold voltage Vth andthe ordinate denotes the number of memory cells. In an embodiment, thememory cells may be single-level cells and be programmed to have a statecorresponding to one of an erase state E and a program state P. Forexample, when a read operation is performed on a memory device, a readvoltage Vr may be applied to a selected word line, and a pass voltageVpass may be applied to an unselected word line. Thus, since the passvoltage Vpass is applied to the unselected word line, memory cellsconnected to the unselected word line may be turned on regardless of thethreshold voltage Vth.

For example, when a program verification operation is performed on thememory device, a program verification voltage Vpgv may be applied to theselected word line, and the pass voltage Vpass may be applied to theunselected word line. For example, when an erase verification operationis performed on the memory device, an erase verification voltage Verymay be applied to the selected word line, and the pass voltage Vpass maybe applied to the unselected word line. However, embodiments are notlimited thereto, and the pass voltage Vpass may be respectivelydifferent in the read operation, the program verification operation, andthe erase operation.

Referring to FIG. 6B, the abscissa denotes a threshold voltage Vth andthe ordinate denotes the number of memory cells. In an embodiment, thememory cells may be multi-level cells and be programmed to have a statecorresponding to one of an erase state E and first to third programstates P1 to P3. For example, when a read operation is performed on thememory device, one of first to third read voltages Vr1, Vr2, and Vr3 maybe applied to the selected word line, and a pass voltage Vpass may beapplied to the unselected word line. Thus, since the pass voltage Vpassis applied to the unselected word line, memory cells connected to theunselected word line may be turned on regardless of the thresholdvoltage Vth.

For instance, when a program verification operation is performed on thememory device, one of first to third program verification voltagesVpgv1, Vpgv2, and Vpgv3 may be applied to the selected word line, and apass voltage Vpass may be applied to the unselected word line. Forexample, when an erase verification operation is performed on the memorydevice, an erase verification voltage Very may be applied to theselected word line, and a pass voltage Vpass may be applied to theunselected word line. However, embodiments are not limited thereto, andthe pass voltage Vpass may be respectively different in the readoperation, the program verification operation, and the erase operation.

As described above, the memory cells may be single-level cells (SLCs) asshown in FIG. 6A or multi-level cells (MLCs) as shown in FIG. 6B.However, embodiments are not limited to the memory cells shown in FIGS.6A and 6B. The memory cells may be triple-level cells (TLCs) capable ofstoring 3-bit data or quad-level cells (QLCs) capable of storing 4-bitdata. Methods of driving word lines according to various embodiments mayalso be applied to TLCs, QLCs, or cells capable of storing data of 5bits or more.

Referring back to FIG. 5, in a first section 21 of sensing time 20, theselected word line voltage V_WLsel may be determined to be a firstvoltage level V1, and voltage generator 130 may provide the firstvoltage level V1 to the selected word line. When a high voltage, such asa pass voltage Vpass, is applied to an adjacent word line, couplingnoise may occur in the selected word line. To inhibit the couplingnoise, the first voltage level V1 may be provided to the selected wordline during first section 21. Thus, first section 21 may be referred toas a “noise inhibition section” or a “noise reduction section.” In anembodiment, first section 21 may be shorter than the first time Ta(i.e., the voltage rise time of an adjacent word line). Thus, anundesired couple-up distortion phenomenon of the adjacent word line maybe improved during a setup operation (e.g., an overdrive operation) ofsecond section 22. However, embodiments are not limited thereto. In someembodiments, a duration of first section 21 may be longer than the firsttime Ta. In some embodiments, first section 21 may be substantiallyequal to the first time Ta.

In second section 22 of sensing time 20, the selected word line voltageV_WLsel may be determined to be a second voltage level V2, and voltagegenerator 130 may provide the second voltage level V2 to the selectedword line. The second voltage level V2 may correspond to an “overdrivevoltage.” Since the second voltage level V2 is applied to the selectedword line, the selected word line may be set to a target voltage levelV_T earlier, thus at least partially compensating for a delay inreaching the target voltage level V_T due to loading of a parasiticcapacitance to one or more adjacent word lines. Thus, second section 22may be referred to as an “overdrive section.” Also, the second voltagelevel V2 may have an offset greater or less than the target voltagelevel V_T. Thus, the second voltage level V2 may be referred to as an“offset pulse.”

In an embodiment, when the target voltage level V_T is greater than thefirst voltage level V1, the second voltage level V2 may be greater thanthe target voltage level V_T. In an embodiment, when the target voltagelevel V_T is less than the first voltage level V1, the second voltagelevel V2 may be less than the target voltage level V_T. As describedabove, control logic circuit 120 may overdrive the selected word line insecond section 22 so that a voltage of the selected word line mayrapidly reach the target voltage level V_T. According to the presentembodiment, since the first voltage level V1 is previously applied tothe selected word line in first section 21, the second voltage level V2may be stably applied to the selected word line in second section 22 sothat an overdrive operation may be efficiently performed.

In third section 23 of sensing time 20, the selected word line voltageV_WLsel may be determined to be the target voltage level V_T, andvoltage generator 130 may provide the target voltage level V_T to theselected word line. Thus, third section 23 may be referred to as a“target section.” In an embodiment, when a read operation is performedon non-volatile memory device 100, the target voltage level V_T may be aread voltage (e.g., Vr of FIG. 6A or Vr1, Vr2, or Vr3 of FIG. 6B). Whenthe read voltage is applied to the selected word line, data written to amemory cell may be read depending on whether the memory cell is on oroff. In some embodiments, the target voltage level V_T for a readoperation (i.e., Vr in FIG. 6A) may be selected to minimize a data readerror rate when reading memory cells, such as a voltage between thedistribution of erased memory cells (“E” in FIG. 6A) and thedistribution of programmed memory cells (“P” in FIG. 6A). Thus, thetarget voltage level V_T may increase or decrease depending on thedistribution of the threshold voltages of the non-volatile memory cellsin non-volatile memory device 100.

In an embodiment, when a program verification operation is performed onnon-volatile memory device 100, the target voltage level V_T may be aprogram verification voltage (e.g., Vpgv of FIG. 6A or Vpgv_1, Vpgv2, orVpgv3 of FIG. 6B). When the program verification voltage is applied tothe selected word line, it may be determined whether a program operationon the memory cell is completed, depending on whether the memory cell ison or off. In an embodiment, when an erase verification operation isperformed on non-volatile memory device 100, the target voltage levelV_T may be an erase verification voltage (e.g., Very of FIG. 6A or FIG.6B). When the erase verification voltage is applied to the selected wordline, it may be determined whether an erase operation on the memory cellis completed, depending on whether the memory cell is on or off. Insimilarity to the explanation above with respect to a read operation,the target voltage level V_T for a program verification operation (i.e.,Vpgv in FIG. 6A) and the target voltage level V_T for an eraseverification operation (i.e., Very in FIG. 6A) may increase or decreasedepending on the distribution of the threshold voltages of thenon-volatile memory cells in non-volatile memory device 100.

When a voltage is applied to the selected word line, a setup time takento reach the target voltage level V_T may vary according to a distancefrom voltage generator 130 to the selected word line. For example, whenthe distance from voltage generator 130 to the selected word line isshort, that is, when the selected word line is a word line near voltagegenerator 130, a word line setup time may be relatively short. Incontrast, when the distance from voltage generator 130 to the selectedword line is long, that is, when the selected word line is a word linefar from voltage generator 130, the word line setup time may berelatively long. However, since the second voltage level V2 is appliedin second section 22 and the target voltage level V_T is then applied inthird section 23, a word line loading time may be reduced regardless ofthe distance between voltage generator 130 and the selected word line.As a result, the sensing performance of non-volatile memory device 100may be improved.

In an embodiment, the first voltage level V1 may be variably determinedaccording to the target voltage level V_T. As the target voltage levelV_T becomes greater, the first voltage level V1 may become greater. Asdescribed above, by determining the first voltage level V1 according tothe target voltage level V_T, an overdrive operation may be efficientlyperformed in second section 22. For example, the target voltage levelV_T may be a positive voltage as described in detail below withreference to FIG. 7.

In FIG. 5, the first voltage level V1 may be less than the targetvoltage level V_T. However, embodiments are not limited thereto. In someembodiments, the first voltage level V1 may be greater than the targetvoltage level V_T as will be described below with reference to FIG. 9.In some embodiments, the target voltage level V_T may be a negativevoltage as described in detail below with reference to FIG. 10.

In an embodiment, a first control time T1 may be variably determinedaccording to the target voltage level V_T. For example, as the targetvoltage level V_T becomes greater, the first control time T1 mayincrease. As described above, by determining the first control time T1according to the target voltage level V_T, an overdrive operation may beefficiently performed in second section 22. In this case, first section21 may correspond to the first control time T1.

In an embodiment, the first control time T1 may include a rise time of aword line voltage and a maintenance time of the word line voltage aswill be described in detail below with reference to FIG. 8. However,embodiments are not limited thereto. In an embodiment, the first controltime T1 may include only the maintenance time of the word line voltageas will be described in detail below with reference to FIG. 11. In anembodiment, as the target voltage level V_T becomes greater, the firstvoltage level V1 may become greater, and a duration of the first controltime T1 may become longer.

FIG. 7 is a diagram of a word line driving operation according to anembodiment. FIG. 7 corresponds to an embodied example of the word linedriving operation shown in FIG. 5, and repeated description thereof willbe omitted.

Referring to FIG. 7, a first target voltage level V_Ta may be less thana second target voltage level V_Tb. For example, the first targetvoltage level V_Ta may correspond to the first read voltage Vr1 of FIG.6B, and the second target voltage level V_Tb may correspond to thesecond read voltage Vr2 of FIG. 6B. When control logic circuit 120performs a sensing operation using the first target voltage level V_Ta,control logic circuit 120 may control a selected word line voltageV_WLsel applied to a selected word line during sensing time 20 as shownby a first curve 210 a. Meanwhile, when control logic circuit 120performs a sensing operation using the second target voltage level V_Tb,control logic circuit 120 may control the selected word line voltageV_WLsel applied to the selected word line during sensing time 20 asshown by a second curve 210 b.

According to first curve 210 a, in first section 21, the selected wordline voltage V_WLsel may be determined to be a first voltage level V1 abased on the first target voltage level V_Ta, and voltage generator 130may provide the first voltage level V1 a to the selected word line.Also, in second section 22, the selected word line voltage V_WLsel maybe determined to be a second voltage level V2 a, and voltage generator130 may provide the second voltage level V2 a to the selected word line.In third section 23, the selected word line voltage V_WLsel may bedetermined to be the first target voltage level V_Ta, and voltagegenerator 130 may provide the first target voltage level V_Ta to theselected word line.

According to second curve 210 b, in first section 21, the selected wordline voltage V_WLsel may be determined to be a first voltage level V1 bbased on the second target voltage level V_Tb, and voltage generator 130may provide the first voltage level V1 b to the selected word line.Also, in second section 22, the selected word line voltage V_WLsel maybe determined to be a second voltage level V2 b, and voltage generator130 may provide the second voltage level V2 b to the selected word line.In third section 23, the selected word line voltage V_WLsel may bedetermined to be the second target voltage level V_Tb, and voltagegenerator 130 may provide the second target voltage level V_Tb to theselected word line.

When comparing first and second curves 210 a and 210 b, the firstvoltage level V1 a may be less than the first voltage level V1 b. Also,the second voltage level V2 a may be less than the second voltage levelV2 b. However, embodiments are not limited thereto, and the secondvoltage levels V2 a and V2 b may be equal to each other. When comparingfirst and second curves 210 a and 210 b, a length of first section 21may be equal to a first control time T1. In this case, the first controltime T1 may be shorter than a first time Ta, which is a rise time of anadjacent word line voltage V_WLadj.

FIG. 8 is a diagram of a word line driving operation according to anembodiment. FIG. 8 corresponds to an embodied example of the word linedriving operation shown in FIG. 5, and repeated description thereof willbe omitted.

Referring to FIG. 8, a first target voltage level V_Ta may be less thana second target voltage level V_Tb. For example, the first targetvoltage level V_Ta may correspond to the first read voltage Vr1 of FIG.6B, and the second target voltage level V_Tb may correspond to thesecond read voltage Vr2 of FIG. 6B. When control logic circuit 120performs a sensing operation using the first target voltage level V_Ta,control logic circuit 120 may control a selected word line voltageV_WLsel, which is applied to a selected word line during a sensing time20, as shown by first curve 210 a. Meanwhile, when control logic circuit120 performs a sensing operation using the second target voltage levelV_Tb, control logic circuit 120 may control the selected word linevoltage V_WLsel, which is applied to the selected word line duringsensing time 20, as shown by a third curve 210 c. The present embodimentcorresponds to a modified example of the word line driving operationshown in FIG. 7, and repeated descriptions thereof will be omitted.

According to first curve 210 a, in a first section 21, the selected wordline voltage V_WLsel may be determined to be a first voltage level V1 a,and a length of first section 21 may be determined to be a first controltime T1 a based on the first target voltage level V_Ta. Thus, voltagegenerator 130 may provide the first voltage level V1 a to the selectedword line during the first control time T1 a. In a second section 22,the selected word line voltage V_WLsel may be determined to be a secondvoltage level V2 a, and a length of second section 22 may be determinedto be a second control time T2 a. Thus, voltage generator 130 mayprovide the selected voltage level V2 a to the selected word line duringthe second control time T2 a. In a third section 23, the selected wordline voltage V_WLsel may be determined to be the first target voltagelevel V_Ta, and voltage generator 130 may provide the first targetvoltage level V_Ta to the selected word line.

According to third curve 210 c, in a first section 21′, the selectedword line voltage V_WLsel may be determined to be the first voltagelevel V1 a, and a length of the first section 21′ may be determined tobe a first control time T1 b based on the second target voltage levelV_Tb. Thus, voltage generator 130 may provide the first voltage level V1a to the selected word line during the first control time T1 b. In asecond section 22′, the selected word line voltage V_WLsel may bedetermined to be a second voltage level V2 b, and a length of secondsection 22′ may be determined to be a second control time T2 b. Thus,voltage generator 130 may provide the second voltage level V2 b to theselected word line during the second control time T2 b. In a thirdsection 23′, the selected word line voltage V_WLsel may be determined tobe the second target voltage level V_Tb, and voltage generator 130 mayprovide the second target voltage level V_Tb to the selected word line.

When comparing first and third curves 210 a and 210 c, the first controltime T1 a may be shorter than the first control time T1 b. Meanwhile,the second control time T2 a may be equal to the second control time T2b. However, embodiments are not limited thereto, and the second controltime T2 a may be different from the second control time T2 b. Inaddition, the second voltage level V2 a may be less than the secondvoltage level V2 b. However, embodiments are not limited thereto, andthe second voltage levels V2 a and V2 b may be equal to each other. Inthis case, each of the first control times T1 a and T1 b may be shorterthan a first time Ta, which is a rise time of an adjacent word linevoltage V_WLadj.

FIG. 9 is a diagram of a word line driving operation according to anembodiment. FIG. 9 corresponds to a modified example of the word linedriving operation shown in FIG. 5, and repeated descriptions thereofwill be omitted.

Referring to FIG. 9, a first voltage level V1′ may be greater than atarget voltage level V_T. For example, the target voltage level V_T maybe a read voltage Vr of FIG. 6A or first to third read voltages Vr1,Vr2, and Vr3 of FIG. 6B. The control logic circuit 120 may control aselected word line voltage V_WLsel, which is applied to a selected wordline during a sensing time 20, as shown by a curve 230.

In first section 21, the selected word line voltage V_WLsel may bedetermined to be a first voltage level V1′ based on a target voltagelevel V_T. Also, in a first section 21, a length of first section 21 maybe determined to be a first control time T1 based on the target voltagelevel V_T. voltage generator 130 may provide a first voltage level V1′to the selected word line during a first control time T1. The firstvoltage level V1′ may be greater than the target voltage level V_T. Thefirst control time T1 may be shorter than a first time Ta. For instance,as the target voltage level V_T becomes greater, the first voltage levelV1′ may become greater, and a duration of the first control time T1 maybecome longer.

In a second section 22, the selected word line voltage V_WLsel may bedetermined to be a second voltage level V2′, and voltage generator 130may provide the second voltage level V2′ to the selected word line. Thesecond voltage level V2′ may be less than the first voltage level V1′and the target voltage level V_T. In a third section 23, the selectedword line voltage V_WLsel may be determined to be target voltage levelV_T, and voltage generator 130 may provide the target voltage level V_Tto the selected word line.

FIG. 10 is a diagram of a word line driving operation according to anembodiment. FIG. 10 corresponds to a modified example of the word linedriving operation shown in FIG. 5, and repeated descriptions thereofwill be omitted.

Referring to FIG. 10, a target voltage level V_T may be a negativevoltage. For example, the target voltage level V_T may be the eraseverification voltage Very of FIG. 6A or FIG. 6B. Thus, when the targetvoltage level V_T is the negative voltage, control logic circuit 120 maycontrol a selected word line voltage V_WLsel, which is applied to aselected word line during a sensing time 20, as shown by a curve 240.

In a first section 21, the selected word line voltage V_WLsel may bedetermined to be a first voltage level V1″ based on a magnitude of thetarget voltage level V_T. Also, in first section 21, a length of firstsection 21 may be determined to be a first control time T1 based on thetarget voltage level V_T. Voltage generator 130 may provide a firstvoltage level V1″ to the selected word line during the first controltime T1. The first voltage level V1″ may be greater than the targetvoltage level V_T. The first control time T1 may be shorter than a firsttime Ta. For instance, as the magnitude of the target voltage level V_Tbecomes greater, the first voltage level V1″ may become greater and/or aduration of the first control time T1 may become longer.

In a second section 22, the selected word line voltage V_WLsel may bedetermined to be a second voltage level V2″, and voltage generator 130may provide the second voltage level V2″ to the selected word line. Thesecond voltage level V2″ may be a negative voltage, and a magnitude ofthe second voltage level V2″ may be greater than that of the targetvoltage level V_T (i.e., V2″ may be more negative than V_T). In a thirdsection 23, the selected word line voltage V_WLsel may be determined tobe the target voltage level V_T, and voltage generator 130 may providethe target voltage level V_T to the selected word line.

FIG. 11 is a diagram of a word line driving operation according to anembodiment. FIG. 11 corresponds to a modified example of the word linedriving operation shown in FIG. 5, and repeated descriptions thereofwill be omitted.

Referring to FIG. 11, a first section 21 may include a voltage rise timeT1 r and a voltage maintenance time T1 m. According to the presentembodiment, a voltage maintenance time T1 m may vary according to atarget voltage level V_T. For example, as the target voltage level V_Tbecomes greater, a duration of the voltage maintenance time T1 m maybecome longer. In this case, the voltage rise time T1 r may be constantregardless of the target voltage level V_T. As a result, a length offirst section 21 may increase with the target voltage level V_T.

FIG. 12 is a diagram showing a word line driving operation when aplurality of sensing operations are performed on an embodiment of anon-volatile memory device 100.

Referring to FIG. 12, a first sensing operation and a second sensingoperation may be sequentially performed on non-volatile memory device100. The first sensing operation may be performed during a first sensingtime 20, and a second sensing operation may be performed during a secondsensing time 30. For example, first sensing time 20 may correspond tosensing time 20 of FIG. 5. A control logic circuit 120 may control aselected word line voltage V_WLsel, which is applied to a selected wordline during first and second sensing times 20 and 30, as shown by afirst curve 310.

Meanwhile, control logic circuit 120 may control an adjacent word linevoltage V_WLadj, which is applied to an adjacent word line during firstand second sensing times 20 and 30, as shown by a second curve 320. Apass voltage Vpass may be applied to the adjacent word line during firstand second sensing times 20 and 30. The pass voltage Vpass may begreater than first and second target voltage levels V_T1 and V_T2. Afirst time Ta may correspond to a voltage rise time of the adjacent wordline, and a second time Tb may correspond to a time for which the passvoltage Vpass is applied to the adjacent word line.

In an embodiment, control logic circuit 120 may control the selectedword line voltage V_WLsel in three stages during first sensing time 20and control the selected word line voltage V_WLsel in two stages duringsecond sensing time 30. A first target voltage level V_T1 of the firstsensing operation may be different from a second target voltage levelV_T2 of the second sensing operation. For example, the first targetvoltage level V_T1 may be greater than the second target voltage levelV_T2. Thus, when a voltage of the adjacent word line rises during thefirst time Ta, the sensing performance of non-volatile memory device 100may be improved using a couple-up phenomenon of the selected word linedue to the adjacent word line. However, embodiments are not limitedthereto, and the first target voltage level V_T1 may be less than thesecond target voltage level V_T2.

In a first section 21 of first sensing time 20, the selected word linevoltage V_WLsel may be determined to be a first voltage level V1 basedon the first target voltage level V_T1. Also, in first section 21, alength of first section 21 may be determined to be a first control timeT1 based on the first target voltage level V_T1. Voltage generator 130may apply the first voltage level V1 to the selected word line duringthe first control time T1 and inhibit coupling noise of the selectedword line due to the adjacent word line.

In a second section 22 of first sensing time 20, the selected word linevoltage V_WLsel may be determined to be a second voltage level V2 thatis different from the first voltage level V1. Voltage generator 130 mayapply the second voltage level V2 to the selected word line andoverdrive the selected word line. In a third section 23 of first sensingtime 20, the selected word line voltage V_WLsel may be determined to bethe first target voltage level V_T1 that is different from the secondvoltage level V2. Voltage generator 130 may apply the first targetvoltage level V_T1 to the selected word line so that the first sensingoperation may be performed on memory cells connected to the selectedword line.

In a first section 31 of second sensing time 30, the selected word linevoltage V_WLsel may be determined to be a third voltage level V3, andvoltage generator 130 may apply the third voltage level V3 to theselected word line and overdrive the selected word line. In a secondsection 32 of second sensing time 30, the selected word line voltageV_WLsel may be determined to be the second target voltage level V_T2that is different from the third voltage level V3. Voltage generator 130may apply the second target voltage level V_T2 to the selected word lineso that the second sensing operation may be performed on the memorycells connected to the selected word line.

In some embodiments, after second sensing time 30, a third sensingoperation may be further performed on non-volatile memory device 100. Inthis case, control logic circuit 120 may control the selected word linevoltage V_WLsel in three stages during first sensing time 20 and controlthe selected word line voltage V_WLsel in two stages during secondsensing time 30. When a third sensing operation is performed aftersecond sensing time 30, control logic circuit 120 may control theselected word line voltage V_WLsel in two stages during the thirdsensing time, too. Thus, when only the first sensing operation isperformed, the control logic circuit 120 may control the selected wordline voltage V_WLsel in three stages. When sensing operations areperformed after the first sensing operation, the selected word linevoltage V_WLsel may be controlled in two stages during each of thesensing operations.

FIG. 13 is a graph showing a program operation of an embodiment of anon-volatile memory device. FIG. 13 shows an example to which a wordline driving method shown in FIG. 12 is applied.

Referring to FIG. 13, a program operation on the non-volatile memorydevice may include a program time 40 and a program verification time 50.In program time 40, a program voltage Vpgm may be applied to a selectedword line connected to a selected memory cell. In program verificationtime 50, a first program verification voltage level V_T1 correspondingto a first target voltage level and a second program verificationvoltage level V_T2 corresponding to a second target voltage level may besequentially applied to the selected word line. For example, the firstprogram verification voltage level V_T1 corresponding to the firsttarget voltage level may be greater than the second program verificationvoltage level V_T2 corresponding to the second target voltage level.

For example, program verification time 50 may include a firstverification time VFY1 and a second verification time VFY2. The firstverification time VFY1 may be divided into a first section 51, a secondsection 52, and a third section 53, which may respectively correspond tofirst to third sections 21, 22, and 23 of first sensing time 20 of FIG.12. In first section 51, at least one of a first voltage level V1applied to the selected word line and a length of first section 51 maybe determined according to the first program verification voltage levelV_T1. The second verification time VFY2 may be divided into a firstsection 54 and a second section 55, which may respectively correspond tofirst and second sections 31 and 32 of second sensing time 30 of FIG.12.

FIG. 14 is a flowchart of a method of operating a non-volatile memorydevice, according to an embodiment.

Referring to FIG. 13, the method of operating the non-volatile memorydevice, according to the present embodiment, may correspond to a methodof driving a selected word line when a sensing operation is performed onthe non-volatile memory device. The method of operating the non-volatilememory device according to the present embodiment may be, for example,sequentially performed in non-volatile memory device 100 of FIG. 1. Theabove descriptions presented with reference to FIGS. 1 to 13 may beapplied to the present embodiment, and repeated descriptions thereofwill be omitted.

In operation S110, in a first section, a first voltage level, which isvariable according to a target voltage level, may be applied to theselected word line. In operation S110, a high voltage, such as a passvoltage, may be applied to an adjacent word line adjacent to theselected word line. When the first voltage level is applied to theselected word line, coupling noise due to the adjacent word line may beinhibited. For example, as the target voltage level becomes greater, thefirst voltage level may become greater. For example, the target voltagelevel may be a positive voltage. For example, the target voltage levelmay be greater than or equal to a critical voltage level. For example,the target voltage level may be a negative voltage. In this case, thefirst voltage level may increase with a magnitude of the target voltagelevel.

In operation S140, in a second section, a second voltage level that isdifferent from the first voltage level may be applied to the selectedword line. By applying the second voltage level to the selected wordline while the first voltage level is being applied to the selected wordline, the selected word line may be stably overdriven. In operationS150, in a third section, the target voltage level that is differentfrom the second voltage level may be applied to the selected word line.Memory cells may be sensed depending on whether memory cells connectedto the selected word line to which the target voltage level is appliedare turned on or off.

FIG. 15 is a flowchart of a method of operating a non-volatile memorydevice, according to an embodiment.

Referring to FIG. 15, the method of operating the non-volatile memorydevice, according to the present embodiment, may correspond to a methodof driving a selected word line when a sensing operation is performed onthe non-volatile memory device, and correspond to a modified example ofthe method shown in FIG. 14. The above descriptions presented withreference to FIGS. 1 to 14 may be applied to the present embodiment, andrepeated descriptions thereof will be omitted.

In operation S120, in a first section that is variable according to atarget voltage level, a first voltage level may be applied to theselected word line. For example, as the target voltage level becomesgreater, a duration of the first section may become longer. For example,the target voltage level may be a positive voltage. For example, thetarget voltage level may be greater than or equal to a critical voltagelevel. For example, the target voltage level may be a negative voltage.In this case, the first section may increase with a magnitude of thetarget voltage level. In operation S140, in a second section, a secondvoltage level that is different from the first voltage level may beapplied to the selected word line. In operation S150, in a thirdsection, the target voltage level that is different from the secondvoltage level may be applied to the selected word line.

FIG. 16 is a flowchart of a method of operating a non-volatile memorydevice, according to an embodiment.

Referring to FIG. 16, the method of operating the non-volatile memorydevice, according to the present embodiment, may correspond to a methodof driving a selected word line when a sensing operation is performed onthe non-volatile memory device, and correspond to a modified example ofthe method shown in FIG. 13 or FIG. 14. The above descriptions presentedwith reference to FIGS. 1 to 15 may be applied to the presentembodiment, and repeated descriptions thereof will be omitted.

In operation S100, as a target voltage level becomes greater, at leastone of a duration of the first section and a first voltage level may bedetermined to be longer or greater. In operation S130, in the firstsection, the first voltage level may be applied to the selected wordline. In operation S140, in a second section, a second voltage levelthat is different from the first voltage level may be applied to theselected word line. In operation S150, in a third section, the targetvoltage level that is different from the second voltage level may beapplied to the selected word line.

FIG. 17 is a flowchart of a method of operating a non-volatile memorydevice, according to an embodiment.

Referring to FIG. 17, the method of operating the non-volatile memorydevice, according to the present embodiment, may correspond to a methodof driving a selected word line when a plurality of sensing operationsare performed on the non-volatile memory device, and correspond to amodified example of the methods shown in FIGS. 14 to 16. The abovedescriptions presented with reference to FIGS. 1 to 16 may be applied tothe present embodiment, and repeated descriptions thereof will beomitted.

In operation S200, as a first target voltage level becomes greater, atleast one of a duration of the first section of a first sensing time anda first voltage level may be determined to be longer or greater. Inoperation S210, in the first section of the first sensing time, thefirst voltage level may be applied to the selected word line. Inoperation S220, in a second section of the first sensing time, a secondvoltage level that is different from the first voltage level may beapplied to the selected word line. In operation S230, in a third sectionof the first sensing time, the first target voltage level that isdifferent from the second voltage level may be applied to the selectedword line so that a first sensing operation may be performed on thenon-volatile memory device.

In operation S240, in a first section of a second sensing time, a thirdvoltage level may be applied to the selected word line. In operationS250, in a second section of the second sensing time, a second targetvoltage level that is different from the third voltage level may beapplied to the selected word line so that a second sensing operation maybe performed on the non-volatile memory device. When a third sensingoperation is performed after the second sensing time, a voltage of theselected word line may be controlled in two stages as shown inoperations S240 and S250.

FIG. 18 is a block diagram of an embodiment of a non-volatile memorydevice 100′.

Referring to FIG. 18, non-volatile memory device 100′ may include amemory cell array 110, a control logic circuit 120′, a voltage generator130′, a row decoder 140, and a page buffer unit 150. Non-volatile memorydevice 100′ according to the present embodiment may correspond to amodified example of non-volatile memory device 100 shown in FIG. 1. Theabove descriptions presented with reference to FIGS. 1 to 17 may beapplied to the present embodiment.

Memory cell array 110 may include a plurality of memory blocks BLK1 toBLKi, and distances between the plurality of memory blocks BLK1 to BLKiand voltage generator 130′ may be different from each other. Forinstance, a distance between the first memory block BLK1 and voltagegenerator 130′ may be shorter than a distance between the i-th memoryblock BLKi and voltage generator 130′. Thus, a loading time of wordlines may be shorter during a sensing operation on the first memoryblock BLK1 than during a sensing operation on the i-th memory blockBLKi.

Referring to FIGS. 5 and 18, during a sensing operation on memory cellarray 110, control logic circuit 120′ may determine at least one of afirst voltage level V1 applied to the selected word line and a firstcontrol time T1 in a first section 21 of a sensing time 20, based on aposition of a memory block or the number of memory blocks driven at thesame time, along with a target voltage level V_T applied to a selectedword line.

For instance, when a first sensing operation is performed on the firstmemory block BLK1, control logic circuit 120′ may divide a first sensingtime for which the first sensing operation is performed, into first tothird sections and control a first selected word line voltage VWLa inthree stages. For example, when a second sensing operation is performedon the i-th memory block BLKi, control logic circuit 120′ may divide asecond sensing time for which the second sensing operation is performed,into first to third sections and control an i-th selected word linevoltage VWLi in three stages.

For example, when a target voltage level V_T applied to the selectedword line in the first sensing operation is equal to a target voltagelevel V_T applied to the selected word line in the second sensingoperation, a voltage level of the first selected word line voltage VWLain the first section may be less than a voltage level of the i-thselected word line voltage VWLi in the first section. Also, a controltime for which the first selected word line voltage VWLa is applied inthe first section may be shorter than a control time for which the i-thselected word line voltage VWLi is applied in the first section.

In an embodiment, during the sensing operation on memory cell array 110,control logic circuit 120′ may differently determine the first voltagelevel V1 applied to the selected word line or the first control time T1in first section 21 of sensing time 20, based on a factor (e.g., athreshold voltage of a selected memory cell), which may affect theloading of a word line, along with the target voltage level V_T appliedto the selected word line. For example, as the threshold voltage of theselected memory cell is reduced, a capacitance of the selected memorycell may increase. Thus, when the target voltage level V_T is the same,as the threshold voltage of the selected memory cell is reduced, thefirst voltage level V1 applied to the selected word line and/or aduration of the first control time T1 may be determined to be greater orlonger in first section 21 of sensing time 20.

In an embodiment, during the sensing operation on memory cell array 110,control logic circuit 120′ may differently determine the first voltagelevel V1 applied to the selected word line or the first control time T1in first section 21 of sensing time 20, based on factors capable ofaffecting the loading of the word line along with the target voltagelevel V_T applied to the selected word line. The factors capable ofaffecting the loading of the word line may include, for example, athreshold voltage of a memory cell adjacent to the selected memory cell.In an embodiment, during the sensing operation on memory cell array 110,control logic circuit 120′ may differently determine the first voltagelevel V1 applied to the selected word line or the first control time T1in first section 21 of sensing time 20, based on factors capable ofaffecting the loading of the word line along with the target voltagelevel V_T applied to the selected word line. The factors capable ofaffecting the loading of the word line may include, for example, atemperature, a count of cycles of program/erase operations, and a kind(SLC or MLC) of memory cells.

As described above, when the voltage of the selected word line iscontrolled in three stages during the sensing operation, the firstvoltage level V1 applied to the selected word line in first section 21and a length of first section 21 may be determined based on a factorcapable of affecting the loading of the word line and the target voltagelevel V_T. The factor capable of affecting the loading of the word linemay include at least one of positions and number of selected word lines,positions and number of memory blocks positions and number of memoryplanes, positions and number of memory chips, the number of data bitswritten to a memory cell, temperature information, a count of cycles ofprogram/erase operations, the number of program loops, a thresholdvoltage of the selected memory cell, a threshold voltage of an adjacentmemory cell, and an operation mode.

FIG. 19 is a block diagram of an embodiment of a non-volatile memorydevice 400.

Referring to FIG. 19, non-volatile memory device 400 may include firstand second memory planes 410 a and 410 b, a control logic circuit 420, avoltage generator 430, first and second row decoders 440 a and 440 b,and first and second page buffer units 450 a and 450 b. However,embodiments are not limited thereto, and non-volatile memory device 400may include a first control logic circuit configured to control firstmemory plane 410 a and a second control logic circuit configured tocontrol second memory plane 410 b instead of control logic circuit 420.Non-volatile memory device 400 according to the present embodiment maycorrespond to a modified example of non-volatile memory device 100 shownin FIG. 1 or non-volatile memory device 100′ shown in FIG. 18. The samedescriptions as with reference to FIGS. 1 to 18 may be applied to thepresent embodiment.

A distance between first memory plane 410 a and voltage generator 430may be different from a distance between second memory plane 410 b andvoltage generator 430. For example, the distance between first memoryplane 410 a and voltage generator 430 may be shorter than the distancebetween second memory plane 410 b and voltage generator 430. Thus, aloading time of word lines may be shorter during a sensing operation onfirst memory plane 410 a than during a sensing operation on secondmemory plane 410 b.

Referring to FIGS. 5 and 19, during the sensing operation on firstmemory plane 410 a, control logic circuit 420 may determine at least oneof a voltage level and an application time of a first selected word linevoltage VWL1 in first section 21 of sensing time 20, based on a targetvoltage level V_T applied to a selected word line. Also, during thesensing operation on second memory plane 410 b, control logic circuit420 may determine at least one of a voltage level and an applicationtime of a second selected word line voltage VWL2 in first section 21 ofsensing time 20, based on the target voltage level V_T applied to theselected word line.

For example, when a first sensing operation is performed on first memoryplane 410 a, control logic circuit 420 may divide a first sensing timefor performing the first sensing operation into first to third sectionsand control the first selected word line voltage VWL1 in three stages.For example, when a second sensing operation is performed on secondmemory plane 410 b, control logic circuit 420 may divide a secondsensing time for performing the second sensing operation into first tothird sections and control the second selected word line voltage VWL2 inthree stages.

For example, when a target voltage level V_T applied to the selectedword line during the first sensing operation is equal to a targetvoltage level V_T applied to the selected word line during the secondsensing operation, a voltage level of the first selected word linevoltage VWL1 in the first section may be less than a voltage level ofthe second selected word line voltage VWL2 in the first section. Also, acontrol time for which the first selected word line voltage VWL1 isapplied in the first section may be shorter than a control time forwhich the second selected word line voltage VWL2 is applied in the firstsection.

FIG. 20 is a block diagram of an example of applying a memory deviceaccording to an embodiment to a solid-state drive (SSD) system 1000.

Referring to FIG. 20, SSD system 1000 may include a host 1100 and an SSD1200. SSD 1200 may transmit and receive signals to and from host 1100through a signal connector and receive power through a power connector.SSD 1200 may include an SSD controller 1210, an auxiliary power supply1220, and memory devices 1230, 1240, and 1250. Memory devices 1230,1240, and 1250 may be vertical-stack-type NAND flash memory devices. Inthis case, SSD 1200 may be implemented using the embodiments describedabove with reference to FIGS. 1 to 19.

FIG. 21 illustrates a memory device 900 having a chip-to-chip structure,according to embodiments.

Referring to FIG. 21, a memory device 900 may have a chip-to-chip (C2C)structure. The C2C structure may refer to a structure formed bymanufacturing an upper chip including a cell region CELL on a firstwafer, manufacturing a lower chip including a peripheral circuit regionPERI on a second wafer, different from the first wafer, and thenconnecting the upper chip and the lower chip in a bonding manner Forexample, the bonding manner may include a method of electricallyconnecting a bonding metal formed on an uppermost metal layer of theupper chip and a bonding metal formed on an uppermost metal layer of thelower chip. For example, when the bonding metals may be formed of copper(Cu), the bonding manner may be a Cu—Cu bonding, and the bonding metalsmay also be formed of aluminum or tungsten. Each memory device of theabove embodiments may be implemented as the memory device 900.

Each of the peripheral circuit region PERI and the cell region CELL ofthe memory device 900 may include an external pad bonding area PA, aword line bonding area WLBA, and a bit line bonding area BLBA.

The peripheral circuit region PERI may include a first substrate 710, aninterlayer insulating layer 715, a plurality of circuit elements 720 a,720 b, and 720 c formed on the first substrate 710, first metal layers730 a, 730 b, and 730 c respectively connected to the plurality ofcircuit elements 720 a, 720 b, and 720 c, and second metal layers 740 a,740 b, and 740 c formed on the first metal layers 730 a, 730 b, and 730c. In an example embodiment, the first metal layers 730 a, 730 b, and730 c may be formed of tungsten having relatively high resistance, andthe second metal layers 740 a, 740 b, and 740 c may be formed of copperhaving relatively low resistance.

In an example embodiment illustrate in FIG. 21, although the first metallayers 730 a, 730 b, and 730 c and the second metal layers 740 a, 740 b,and 740 c are shown and described, they are not limited thereto, and oneor more metal layers may be further formed on the second metal layers740 a, 740 b, and 740 c. At least a portion of the one or more metallayers formed on the second metal layers 740 a, 740 b, and 740 c may beformed of aluminum or the like having a lower resistance than those ofcopper forming the second metal layers 740 a, 740 b, and 740 c.

The interlayer insulating layer 715 may be disposed on the firstsubstrate 710 and cover the plurality of circuit elements 720 a, 720 b,and 720 c, the first metal layers 730 a, 730 b, and 730 c, and thesecond metal layers 740 a, 740 b, and 740 c. The interlayer insulatinglayer 715 may include an insulating material such as silicon oxide,silicon nitride, or the like.

Lower bonding metals 771 b and 772 b may be formed on the second metallayer 740 b in the word line bonding area WLBA. In the word line bondingarea WLBA, the lower bonding metals 771 b and 772 b in the peripheralcircuit region PERI may be electrically connected to c in a bondingmanner, and the lower bonding metals 771 b and 772 b and the upperbonding metals 871 b and 872 b may be formed of aluminum, copper,tungsten, or the like. Further, the upper bonding metals 871 b and 872 bin the cell region CELL may be referred as first metal pads and thelower bonding metals 771 b and 772 b in the peripheral circuit regionPERI may be referred as second metal pads.

The cell region CELL may include at least one memory block. The cellregion CELL may include a second substrate 810 and a common source line820. On the second substrate 810, a plurality of word lines 831 to 838(i.e., 830) may be stacked in a direction (a Z-axis direction),perpendicular to an upper surface of the second substrate 810. At leastone string select line and at least one ground select line may bearranged on and below the plurality of word lines 830, respectively, andthe plurality of word lines 830 may be disposed between the at least onestring select line and the at least one ground select line.

In the bit line bonding area BLBA, a channel structure CH may extend ina direction, perpendicular to the upper surface of the second substrate810, and pass through the plurality of word lines 830, the at least onestring select line, and the at least one ground select line. The channelstructure CH may include a data storage layer, a channel layer, a buriedinsulating layer, and the like, and the channel layer may beelectrically connected to a first metal layer 850 c and a second metallayer 860 c. For example, the first metal layer 850 c may be a bit linecontact, and the second metal layer 860 c may be a bit line. In anexample embodiment, the bit line 860 c may extend in a first direction(a Y-axis direction), parallel to the upper surface of the secondsubstrate 810.

In an example embodiment illustrated in FIG. 21, an area in which thechannel structure CH, the bit line 860 c, and the like are disposed maybe defined as the bit line bonding area BLBA. In the bit line bondingarea BLBA, the bit line 860 c may be electrically connected to thecircuit elements 720 c providing a page buffer 893 in the peripheralcircuit region PERI. For example, the bit line 860 c may be connected toupper bonding metals 871 c and 872 c in the cell region CELL, and theupper bonding metals 871 c and 872 c may be connected to lower bondingmetals 771 c and 772 c connected to the circuit elements 720 c of thepage buffer 893.

In the word line bonding area WLBA, the plurality of word lines 830 mayextend in a second direction (an X-axis direction), parallel to theupper surface of the second substrate 810, and may be connected to aplurality of cell contact plugs 841 to 847 (i.e., 840). The plurality ofword lines 830 and the plurality of cell contact plugs 840 may beconnected to each other in pads provided by at least a portion of theplurality of word lines 830 extending in different lengths in the seconddirection. A first metal layer 850 b and a second metal layer 860 b maybe connected to an upper portion of the plurality of cell contact plugs840 connected to the plurality of word lines 830, sequentially. Theplurality of cell contact plugs 840 may be connected to the circuitregion PERI by the upper bonding metals 871 b and 872 b of the cellregion CELL and the lower bonding metals 771 b and 772 b of theperipheral circuit region PERI in the word line bonding area WLBA.

The plurality of cell contact plugs 840 may be electrically connected tothe circuit elements 720 b providing a row decoder 894 in the peripheralcircuit region PERI. In an example embodiment, operating voltages of thecircuit elements 720 b providing the row decoder 894 may be differentthan operating voltages of the circuit elements 720 c providing the pagebuffer 893. For example, operating voltages of the circuit elements 720c providing the page buffer 893 may be greater than operating voltagesof the circuit elements 720 b providing the row decoder 894.

A common source line contact plug 880 may be disposed in the externalpad bonding area PA. The common source line contact plug 880 may beformed of a conductive material such as a metal, a metal compound,polysilicon, or the like, and may be electrically connected to thecommon source line 820. A first metal layer 850 a and a second metallayer 860 a may be stacked on an upper portion of the common source linecontact plug 880, sequentially. For example, an area in which the commonsource line contact plug 880, the first metal layer 850 a, and thesecond metal layer 860 a are disposed may be defined as the external padbonding area PA.

Input-output pads 705 and 805 may be disposed in the external padbonding area PA. Referring to FIG. 21, a lower insulating film 701covering a lower surface of the first substrate 710 may be formed belowthe first substrate 710, and a first input-output pad 705 may be formedon the lower insulating film 701. The first input-output pad 705 may beconnected to at least one of the plurality of circuit elements 720 a,720 b, and 720 c disposed in the peripheral circuit region PERI througha first input-output contact plug 703, and may be separated from thefirst substrate 710 by the lower insulating film 701. In addition, aside insulating film may be disposed between the first input-outputcontact plug 703 and the first substrate 710 to electrically separatethe first input-output contact plug 703 and the first substrate 710.

Referring to FIG. 21, an upper insulating film 801 covering the uppersurface of the second substrate 810 may be formed on the secondsubstrate 810, and a second input-output pad 805 may be disposed on theupper insulating layer 801. The second input-output pad 805 may beconnected to at least one of the plurality of circuit elements 720 a,720 b, and 720 c disposed in the peripheral circuit region PERI througha second input-output contact plug 803.

According to embodiments, the second substrate 810 and the common sourceline 820 may not be disposed in an area in which the second input-outputcontact plug 803 is disposed. Also, the second input-output pad 805 maynot overlap the word lines 830 in the third direction (the Z-axisdirection). Referring to FIG. 21, the second input-output contact plug803 may be separated from the second substrate 810 in a direction,parallel to the upper surface of the second substrate 810, and may passthrough the interlayer insulating layer 815 of the cell region CELL tobe connected to the second input-output pad 805.

According to embodiments, the first input-output pad 705 and the secondinput-output pad 805 may be selectively formed. For example, the memorydevice 900 may include only the first input-output pad 705 disposed onthe first substrate 710 or the second input-output pad 805 disposed onthe second substrate 810. Alternatively, the memory device 900 mayinclude both the first input-output pad 705 and the second input-outputpad 805.

A metal pattern in an uppermost metal layer may be provided as a dummypattern or the uppermost metal layer may be absent, in each of theexternal pad bonding area PA and the bit line bonding area BLBA,respectively included in the cell region CELL and the peripheral circuitregion PERI.

In the external pad bonding area PA, the memory device 900 may include alower metal pattern 773 a, corresponding to an upper metal pattern 872 aformed in an uppermost metal layer of the cell region CELL, and havingthe same shape as the upper metal pattern 872 a of the cell region CELL,in an uppermost metal layer of the peripheral circuit region PERI. Inthe peripheral circuit region PERI, the lower metal pattern 773 a formedin the uppermost metal layer of the peripheral circuit region PERI maynot be connected to a contact. Similarly, in the external pad bondingarea PA, an upper metal pattern, corresponding to the lower metalpattern formed in an uppermost metal layer of the peripheral circuitregion PERI, and having the same shape as a lower metal pattern of theperipheral circuit region PERI, may be formed in an uppermost metallayer of the cell region CELL.

The lower bonding metals 771 b and 772 b may be formed on the secondmetal layer 740 b in the word line bonding area WLBA. In the word linebonding area WLBA, the lower bonding metals 771 b and 772 b of theperipheral circuit region PERI may be electrically connected to theupper bonding metals 871 b and 872 b of the cell region CELL by a Cu—Cubonding.

Further, the bit line bonding area BLBA, an upper metal pattern 892,corresponding to a lower metal pattern 752 formed in the uppermost metallayer of the peripheral circuit region PERI, and having the same shapeas the lower metal pattern 752 of the peripheral circuit region PERI,may be formed in an uppermost metal layer of the cell region CELL. Acontact may not be formed on the upper metal pattern 892 formed in theuppermost metal layer of the cell region CELL.

In an example embodiment, corresponding to a metal pattern formed in anuppermost metal layer in one of the cell region CELL and the peripheralcircuit region PERI, a reinforcement metal pattern having the same shapeas the metal pattern may be formed in an uppermost metal layer inanother one of the cell region CELL and the peripheral circuit regionPERI, and a contact may not be formed on the reinforcement metalpattern.

Typical example embodiments of the inventive concept are disclosed inthe above description and the drawings. Although specific terms areemployed, they are used in a generic and descriptive sense only and notfor purposes of limitation. It will be understood by those of ordinaryskill in the art that various changes in form and details may be made tothe disclosed embodiments without departing from the spirit and scope ofthe inventive concept as defined by the following claims.

What is claimed is:
 1. A method of operating a non-volatile memorydevice, the non-volatile memory device comprising a memory cell regionincluding a first metal pad, and a peripheral circuit region including asecond metal pad and vertically connected to the memory cell region bythe first metal pad and the second metal pad, the method comprising:performing a first sensing operation on the non-volatile memory deviceduring a first sensing time including a first section, a second section,and a third section, wherein the performing of the first sensingoperation comprises: applying a first voltage level to a selected wordline in the first section, wherein the first voltage level is variableaccording to a first target voltage level; applying a second voltagelevel to the selected word line in the second section, wherein thesecond voltage level is different from the first voltage level; andapplying the first target voltage level to the selected word line in thethird section, wherein the first target voltage level is different fromthe second voltage level, wherein the first voltage level becomesgreater as the first target voltage level becomes greater.
 2. The methodof claim 1, wherein the first sensing operation corresponds to one of aread operation, a program verification operation, and an eraseverification operation, wherein the first target voltage levelcorresponds to one of a read voltage, a program verification voltage,and an erase verification voltage according to an operation mode of thenon-volatile memory device.
 3. The method of claim 1, wherein a durationof the first section becomes longer as the first target voltage levelbecomes greater.
 4. The method of claim 1, wherein the first sectioncomprises a voltage rise time and a voltage maintenance time, whereinthe voltage maintenance time becomes longer as the first target voltagelevel becomes greater.
 5. The method of claim 1, before the applying ofthe first voltage level to the selected word line, further comprising atleast one of operations of: determining the first voltage level to begreater as the first target voltage level becomes greater; anddetermining a duration of the first section to be longer as the firsttarget voltage level becomes greater.
 6. The method of claim 1, whereinthe first section is shorter than a voltage rise time of an adjacentword line adjacent to the selected word line.
 7. The method of claim 6,wherein the performing of the first sensing operation further comprisesapplying a pass voltage to the adjacent word line after the voltage risetime of the adjacent word line.
 8. The method of claim 1, furthercomprising, before the applying of the first voltage level to theselected word line, determining at least one of the first section andthe first voltage level, based on one or more factors capable ofaffecting loading of word lines and the first target voltage level,wherein the factors include at least one of positions and number ofselected word lines, positions and number of memory blocks including theselected word lines, positions and number of memory planes including theselected word lines, positions and number of memory chips including theselected word lines, a number of data bits written to a selected memorycell, temperature information, a count of cycles of program/eraseoperations on the selected memory cell, a number of program loops, athreshold voltage of the selected memory cell, a threshold voltage of anadjacent memory cell adjacent to the selected memory cell, and anoperation mode of the non-volatile memory device.
 9. The method of claim1, wherein the first target voltage level has a positive voltage. 10.The method of claim 1, wherein the second voltage level is greater thanthe first voltage level and the first target voltage level.
 11. Themethod of claim 1, wherein the second voltage level is less than thefirst voltage level and the first target voltage level.
 12. The methodof claim 1, further comprising, after the performing of the firstsensing operation, performing a second sensing operation on thenon-volatile memory device during a second sensing time, the secondsensing time including first and second sections, wherein the performingof the second sensing operation comprises: applying a third voltagelevel to the selected word line in the first section of the secondsensing time; and applying a second target voltage level to the selectedword line in the second section of the second sensing time, whichfollows the first section of the second sensing time, wherein the secondtarget voltage level is different from the third voltage level.
 13. Amethod of operating a non-volatile memory device, the non-volatilememory device comprising a memory cell region including a first metalpad, and a peripheral circuit region including a second metal pad andvertically connected to the memory cell region by the first metal padand the second metal pad, the method comprising: performing a firstsensing operation on the non-volatile memory device during a firstsensing time; and performing a second sensing operation on thenon-volatile memory device during a second sensing time after the firstsensing time, wherein the performing of the first sensing operationcomprises: applying a first voltage level to a selected word line in afirst section of the first sensing time; applying a second voltage levelto the selected word line in a second section of the first sensing time,which follows the first section of the first sensing time, wherein thesecond voltage level is different from the first voltage level; andapplying a first target voltage level to the selected word line in athird section of the first sensing time, which follows the secondsection of the first sensing time, wherein the first target voltagelevel is different from the second voltage level, wherein as the firsttarget voltage level becomes greater, a duration of the first sectionbecomes longer or the first voltage level becomes greater.
 14. Anon-volatile memory device, comprising: a memory cell region including afirst metal pad; a peripheral circuit region including a second metalpad and vertically connected to the memory cell region by the firstmetal pad and the second metal pad; a memory cell array in the memorycell region, the memory cell array including a plurality of word linesand memory cells each connected to one of the word lines; a controllogic circuit in the peripheral circuit region, the control logiccircuit being configured to select a selected word line among theplurality of word lines in response to an address received by thecontrol logic circuit, to determine a target voltage level to be appliedto the selected word line as a selected word line voltage for a sensingoperation during a first sensing time in order to perform a memoryoperation on a selected memory cell connected to the selected word line,the control logic circuit being further configured to: cause theselected word line voltage to be a first voltage level in a firstsection of the first sensing time, cause the selected word line voltageto be a second voltage level in a second section of the first sensingtime which immediately follows the first section of the first sensingtime, wherein the second voltage is different than the first voltagelevel, and cause the selected word line voltage to be the target voltagelevel in a third section of the first sensing time which immediatelyfollows the second section of the first sensing time, wherein the targetvoltage level is different than the second voltage level; and a voltagegenerator in the peripheral circuit region, the voltage generator beingconfigured to generate the selected word line voltage in the first,second, and third sections of the sensing time in response to thecontrol logic circuit.
 15. The non-volatile memory device of claim 14,wherein the control logic circuit is further configured to adjust atleast one of the first voltage and a duration of the first section inresponse to the target voltage.
 16. The non-volatile memory device ofclaim 14, wherein the control logic circuit is further configured toselect a plurality of other selected word lines, adjust at least one ofthe first voltage and a duration of the first section in based on one ormore factors capable of affecting loading of the selected word line andthe target voltage level, wherein the factors include at least one ofpositions and a number of the selected word lines, positions and numberof memory blocks in the memory cell array including the selected wordlines, positions and number of memory planes including the selected wordlines, positions and number of memory chips including the selected wordlines, a number of data bits written to the selected memory cell,temperature information, a count of cycles of program/erase operationson the selected memory cell, a number of program loops, a thresholdvoltage of the selected memory cell, a threshold voltage of an adjacentmemory cell adjacent to the selected memory cell, and an operation modeof the non-volatile memory device.
 17. The non-volatile memory device ofclaim 14, wherein the memory operation is one of a read operation, aprogram verification operation, and an erase verification operation, andwherein the target voltage level corresponds to one of a read voltage, aprogram verification voltage, and an erase verification voltagecorresponding to an operation mode of the non-volatile memory device.18. The non-volatile memory device of claim 14, wherein the first metalpad and the second metal pad formed of copper.
 19. The non-volatilememory device of claim 14, wherein the first metal pad and the secondmetal pad are connected by bonding manner
 20. The non-volatile memorydevice of claim 14, wherein the memory cell region is formed on a firstwafer and the peripheral circuit region is formed on a second wafer.